1. Field of the Invention
The present invention relates in general to a CMOS constant current reference circuit suitable for use with a Rambus DRAM. More specifically, the invention relates to a CMOS constant current reference circuit capable of providing a constant current to a load, regardless of a variation in supply voltage and a variation in temperature.
2. Description of the Related Art
FIG. 1 (Prior Art) is a conventional constant current reference circuit using a CMOS transistor and a bipolar transistor. The conventional constant current reference circuit includes a negative current generating unit 10 for generating a first current I1 having a negative (xe2x88x92) coefficient, a first positive current generating unit 20 for generating a second current I2 having a positive (+) coefficient, a second positive current generating unit 30 for generating a third current I3 having a positive (+) coefficient, and a current summing circuit 40 for summing together the first current I1, having a negative (xe2x88x92) coefficient and the second current I2 having a positive (+) coefficient, thereby generating a constant bias current Ibias.
The negative current generating unit 10 includes a PMOS transistor MP3 adapted to transmit a supply voltage VDD to a node Nd1 in response to a signal from the node Nd1, and an NMOS transistor MN3 adapted to supply the signal from the node Nd1 to a resistor R1 coupled to a ground voltage Vss in response to a signal from a node Nd3.
The first positive current generating unit 20 includes a PMOS transistor MP2 adapted to supply the supply voltage VDD to a node Nd2 in response to a signal from the node Nd2. The first positive current generating unit 20 also includes an NMOS transistor MN2, a resistor R2, and a PNP type bipolar transistor Q1 connected in series between the node Nd2 and the ground voltage Vss. The NMOS transistor MN2 serves to supply the signal from the node Nd2 to the resistor R2 in response to the signal from the Nd3. The PNP type bipolar transistor Q1 is coupled at the base thereof to the ground voltage Vss, so that it is always in an ON state thereof.
The second positive current generating unit 30 includes a PMOS transistor MP1 adapted to supply the supply voltage VDD to the node Nd3 in response to the signal from the node Nd2. The second positive current generating unit 30 also includes an NMOS transistor MN1 and a PNP type bipolar transistor Q2 connected in series between the node Nd3 and the ground voltage Vss. The NMOS transistor MN1 serves to supply the signal from the Nd3 to the emitter of the PNP type bipolar transistor Q2 in response to the signal from the node Nd3. The PNP type bipolar transistor Q2 is coupled at the base thereof to the ground voltage Vss, so that it is always in an ON state.
The current summing circuit unit 40 includes a PMOS transistor MP4 adapted to supply the supply voltage VDD to a node Nd4 in response to the signal from the node Nd1, a PMOS transistor MP5 adapted to supply the supply voltage VDD to the node Nd4 in response to the signal from the node Nd2, and an NMOS transistor MN4 adapted to discharge a voltage from the node Nd4 in response to a bias current Ibias applied to the node Nd4. The bias current Ibias flowing through the node Nd4 has a constant value corresponding to the sum of a current I1, having a negative (xe2x88x92) coefficient, supplied through the PMOS transistor MP4 and a current I2, having a positive (+) coefficient, supplied through the PMOS transistor MP5.
Now, the operation of the conventional constant current reference circuit having the above mentioned configuration will be described. For the current I2 flowing through the resistor R2 in a loop including the PNP type bipolar transistor Q1, resistor R2, NMOS transistors MN2 and MN1, and PNP type bipolar transistor Q2, the following equations apply:
VBE2=I2xc3x97R2+VBE1
I2=(VBE2xe2x88x92VBE1)/R2
Hence,
VBE2=(kT/q)ln(I2/I3), VBE1=(kT/q)ln(I1/I3)
I2=(kT/qR2)ln(I2/I1)
In the above equations, xe2x80x9cVBE2xe2x80x9d represents a voltage applied across the PNP type bipolar transistor Q2 between the emitter and base thereof, and xe2x80x9ckT/qxe2x80x9d represents a thermal voltage VT depending on a temperature coefficient TC (VT=kT/q), where xe2x80x9ckxe2x80x9d is Boltzmann""s constant, xe2x80x9cTxe2x80x9d is the absolute temperature in Kelvin and xe2x80x9cqxe2x80x9d is the magnitude of the electronic charge.
Accordingly, the current source of the current I2, which has a positive (+) coefficient, can be derived, based on a temperature. The current I2 is mirrored to the PMOS transistor MP5 by the PMOS transistor MP2. For the current I1 flowing through the resistor R1 in a loop including the NMOS transistors MN3 and MN1, and PNP type bipolar transistor Q2, the following equations apply:
VBE2=I1xc3x97R1
I1=VBE2/R1
I1=(kT/qR1)ln(I2/I3)
Accordingly, the current source of the current I1, which has a negative (xe2x88x92) coefficient, can be derived, based on a temperature. The current I1 is mirrored to the PMOS transistor MP4 by the PMOS transistor MP3.
The current summing circuit, which consists of the PMOS transistors MP4 and MP5, and the NMOS transistor MN4, generates a constant bias current Ibias by summing together the mirrored current I1 having a negative (xe2x88x92) coefficient and the mirrored current I2 having a positive (+) coefficient.
This bias current Ibias can be expressed as follows:
Ibias=I1+I2=(VBE2/R1)+(xcex94VBE/R2)
xcex94VBE=VBE2xe2x88x92VBE1
However, the above mentioned conventional constant current reference circuit, which uses the bipolar transistors Q1 and Q2 respectively adapted to generate currents having positive (+) and negative (xe2x88x92) coefficients depending on an increase in temperature, has a problem in that when a negative (xe2x88x92) current source is formed depending on an increase in temperature, by use of the bipolar transistors Q1 and Q2, it is necessary to extract model parameters by individually forming respective patterns of the bipolar transistors Q1 and Q2 in the manufacture of MOS transistors. Furthermore, the integration of the constant current reference circuit into a chip is uneconomical because the constant current reference circuit occupies a chip area considerably larger than that of the MOS transistors. Where the constant current reference circuit is used to generate a voltage reference, an increased variation in voltage is exhibited due to an increased variation in current resulting from a high temperature coefficient. For this reason, there is a problem in that a degradation in output occurs in the case of a system requiring a precise output.
The conventional constant current reference circuit has a problem in that it requires a number of transistors because it should have not only the circuits for generating the negative (xe2x88x92) current I1 and the positive (+) current I2, respectively, but also the circuit for generating the constant bias current based on the sum of the currents I1 and I2 having respective positive (+) and negative (xe2x88x92) coefficients.
According to one aspect of the invention, there is provided a CMOS constant current reference circuit having a simple circuit configuration, wherein the only transistors are CMOS transistors. There are no bipolar transistors. The circuit configuration is capable of providing a constant current to a load, regardless of a variation in supply voltage and a variation in temperature.
A constant current generating means generates a constant bias current regardless of a variation of a supply voltage. A self compensation means controls the bias current generating means to maintain the bias current generated therefrom at a constant level regardless of a variation in temperature. A starting means establishes a current path adapted to activate the constant current generating means. A constant current supply means supplies the bias current generated from the constant current generating means, in a constant amount.
The constant current generating means comprises a first PMOS transistor and a second PMOS transistor respectively adapted to supply the supply voltage to a first node and a second node at constant levels in accordance with a voltage level at the second node, and a first NMOS transistor and a second NMOS transistor respectively adapted to discharge voltages from the first and second nodes into a ground voltage, the first and second PMOS transistors being a current mirror structure and the first and second NMOS transistors being a current mirror structure.
The constant current generating means further comprises a variable resistor coupled between the second NMOS transistor and the ground voltage and adapted to control a parameter depending on a process variation. The self compensation means comprises a PMOS transistor coupled between the first node and the ground voltage while having a diode structure. The starting means comprises an NMOS transistor coupled between the supply voltage and the first node while having a diode structure. The constant current supply means comprises NMOS transistors being a current mirror structure.